Control of removal rates in CMP

ABSTRACT

A two-step method for chemical mechanical polishing of a semiconductor substrate having successive layers, comprised of, a metal layer, an underlying barrier film and an underlying dielectric layer. The first polishing step is performed utilizing a slurry composition selective to the metal in the metal layer, to remove the metal at a high removal rate during polishing, and the second polishing step is performed utilizing a slurry composition selective to the barrier film and least selective to the metal layer and the underlying dielectric layer. In an alternate embodiment, the second polishing step is performed with a slurry equally selective to the barrier layer and the underlying dielectric layer and least selective to the metal of the metal layer, to remove the barrier layer at a high removal rate during polishing, and level a surface of the dielectric layer to the surface of the metal interconnection structure in the underlying dielectric layer.

[0001] This application is a continuation-in-part of application Ser.No. 09/693,211, filed Oct. 20, 2000, which claims the benefit ofProvisional Application 60/161,242, filed Oct. 22, 1999. Thisapplication is a continuation-in-part of application Ser. No. 09/329,225filed Jun. 10, 1999, which claims the benefit of Provisional Application60/088,849 filed Jun. 10, 1998. This application is acontinuation-in-part of application Ser. No. 09/420,682 filed Oct. 19,1999, which claims the benefit of Provisional Application 60/104,876filed Oct. 20, 1998. This application is a continuation-in-part ofapplication Ser. No. 09/439,461 filed Nov. 15, 1999, which claims thebenefit of Provisional Application serial number 60/108,656 filed Nov.16, 1998. This application also claims the benefit of ProvisionalApplication 60/188,421 filed Mar. 10, 2000.

[0002] This invention pertains to polishing methods and slurrycompositions or formulations that are used in polishing a semiconductorsubstrate having successive layers, comprised of, a metal layer, anunderlying barrier film or layer, and an underlying dielectric layer.

[0003] Landers et al. in U.S. Pat. No. 5,676,587 discloses a two-stepchemical mechanical polishing process for polishing a semiconductorsubstrate. The first polishing step utilizes an alumina-based slurry toremove a metal layer from an underlying barrier film. The secondpolishing step utilizes a silica-based slurry to remove the barrier filmof tantalum(Ta), tantalum nitride (TaN), titanium (Ti), or titaniumnitride (TiN). The silica-based slurry used in the second polishing stepis pH neutral and is selective to Ta, TaN, Ti, or TiN to remove thebarrier film.

[0004] Chemical mechanical polishing (CMP) is an enabling technology forthe production of complex and dense semiconductor structures and is aneffective method for the removal and planarization of thin films orlayers on semiconductor substrates during the production ofsemiconductor structures containing integrated circuits such asmulti-chip modules, capacitors and the like. During the CMP process, achemical slurry or polishing fluid (referred to herein as slurry) isused along with a polishing pad. The mechanical motion of the polishingpad relative to the semiconductor substrate in combination with chemicalreaction of the polishing fluid with the substrate surface results inmaterial removal from the semiconductor substrate surface. The“damascene” CMP process is employed for forming interconnect lines andvias for multi-layer metal structures that provide the “wiring” of anintegrated circuit and involves etching trenches in a planar dielectric(insulator) layer and filling the trenches with a conductive material.The conductive material is typically a metal such as aluminum, copper,or tungsten. To ensure complete filling of trenches, an overlayer ofmetal, about 10,000 to 15,000 Angstrom in thickness, is required. Thedielectric is typically silicon dioxide (SiO₂), silicon dioxide derivedfrom tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), boronphosphosilicate glass (BPSG), or a low-k dielectric. A technique called“dual-damascene” adds etched vias for providing contact to a lower levelas the upper damascene structure is filled. More details are found in“Making the Move to Dual Damascene Processing,” SemiconductorInternational, August 1997. Typically a layer of another material isfirst deposited to line the trenches and vias to prevent the migrationof metal ions into the dielectric layer. This migration barrier orbarrier layer (also referred to as a liner layer) typically comprisestantalum, tantalum nitride, titanium and/or titanium nitride. One ormore barrier layers may be provided depending on the specificapplication. The barrier layer has a thickness up to about 1,000Angstroms. CMP of such a substrate is performed in two steps to obtain apolished structure with metal circuit interconnect lines in thedielectric layer to generate an integrated circuit.

[0005] As described above, semiconductor substrates used to makeintegrated circuits typically contain three different layers: aconductive metal layer, a barrier (or liner) film between the conductivemetal layer and the underlying dielectric layer, and an underlyingdielectric layer. While polishing a semiconductor substrate by CMP, itis desirable for the removal rates of each layer to differ significantlyfrom each other in order to induce planarity and maintain the integrityof the semiconductor substrate during polishing. This difference inremoval rates is characterized by a parameter termed the selectivityratio. For example, the ratio of metal removal rate to the dielectricremoval rate is termed the metal-dielectric selectivity ratio. It isalso critical to maintain the cross section and planarity of underlyingconducting metal interconnect structures (trenches or lines) thatprovide metal circuit interconnect structures for the integratedcircuit, especially when polishing to attain high removal rates of thevarious layers. Excessive removal of metal from the conducting metallines is observed as cavities (known as “dishing”) and is undesirable,since it affects the electrical performance of the semiconductorstructure (integrated circuit) resulting from CMP of the semiconductorsubstrate. Similarly, excessive removal of the dielectric layersurrounding the metal lines is observed as cavities (known as “erosion”)and is undesirable, since the dielectric layer should be flawless andfree of cavities, adjacent to the side geometry of the metal lines toensure optimal electrical performance of the semiconductor structure(integrated circuit) resulting from CMP of the semiconductor substrate.Further, CMP polishing is required to polish the semiconductor substratewith a smooth planar polished surface on which are manufacturedsuccessive layers, which themselves are polished by CMP. Thus, excessivedishing and erosion in the underlying layers manifests as defects in theupper layers.

[0006] During known CMP, the semiconductor substrate (substrate) to bepolished is mounted on a carrier or polishing head of a polishingmachine. The exposed surface of the substrate is placed against arotating polishing pad. The surface of the polishing pad that is incontact with the semiconductor substrate is referred to as the polishinglayer. The polishing pad may be a standard pad (without any abrasive inthe polishing layer) also referred to as a non fixed-abrasive pad or afixed-abrasive pad (containing abrasive in the polishing layer). Thecarrier head provides a controllable pressure (or downforce), on thesubstrate to bias it towards the polishing pad. A polishing fluid withor without abrasive particles is then dispensed at the interface of thewafer and the polishing pad to enhance removal of the target layer (fore.g., metal layer in first-step CMP or barrier layer in second-stepCMP). The polishing fluid is preferably water based and may or may notrequire the presence of abrasive particles, depending on the compositionof the polishing layer of the polishing pad. An abrasive-free polishingfluid also referred to as a reactive liquid is typically used with afixed-abrasive pad while a polishing fluid containing abrasive particlesis typically used with a non fixed-abrasive pad. For polishing softermetal interconnects, such as copper, the polishing fluid can contain upto 3% by weight of abrasive particles.

[0007] A need exists for a method of polishing by CMP to selectivelyremove (1) the metal layer and the barrier film while minimizing erosionof the dielectric layer in a semiconductor substrate; or (2) selectivelyremove the barrier film and dielectric layer while minimizing dishing ofmetal in metal lines (trenches) in a semiconductor substrate.

[0008] A method according to this invention, comprises a two-step CMPprocess for polishing a semiconductor substrate containing a conductingmetal layer, a dielectric layer, and a barrier film or layer between thetwo. In the first step of the CMP process, the metal layer is removedfrom the substrate without removing significant amounts of either thebarrier film or the underlying dielectric layer. In the second step ofthe CMP process, the barrier film is removed selectively from anunderlying dielectric layer, with minimal removal of metal providingmetal lines in the underlying dielectric layer, utilizing a slurryaccording to this invention, resulting in a smooth planar polishedsurface.

[0009] In an alternate embodiment, the second step of the CMP process isperformed utilizing a slurry according to this invention that is equallyhighly selective for removal of the barrier film and the dielectriclayer but relatively much less selective for removal of the metalproviding metal lines in the underlying dielectric layer. In thisalternate embodiment, the method of this invention removes any scratchesor defects in the underlying dielectric layer.

[0010] The method of this invention is applicable to any semiconductorsubstrate containing: a conductive metal (such as Cu, Al, W, Pt, Pd, Au,or Ir), a barrier or liner layer (such as Ta, TaN, Ti, or TiN), and anunderlying dielectric layer (such as SiO₂, TEOS, PSG, BPSG, or any low-kdielectric). Metal line widths, or features, on semiconductor substratesare often around 5 μ. However, new technologies are allowing the size offeatures to decrease to about 0.18 μ. Such newer, smaller features alongwith higher feature densities will require more sophisticated andspecialized slurries. The method of this invention is suitably performedon a substrate with line widths of about 0.1, 0.13, 0.15, 0.2, 0.25,0.3, 0.35, 0.4, 0.45 to 0.5 μ. Suitably, the present method is performedon a substrate with line widths of less than 0.4 μ, suitably less than0.3 μ, suitably less than 0.2 μ, and suitably about 0.18 μ.

[0011] In an embodiment, the method of this invention is used to polisha substrate containing a Cu metal layer, an underlying Ta or TaN barrierlayer, and a SiO₂ dielectric layer, by a two-step CMP process. In thefirst step, the Cu overburden layer is removed while removing minimalamounts of the Ta /TaN liner or SiO₂. The slurry used in the first stepof this process is any conventional slurry that is capable of removingthe copper metal overburden layer covering the semiconductor structure,and has a very low rate of material removal on the Ta/TaN barrier filmlayer and underlying SiO₂ layer. Typically, a conventional first stepslurry has an acidic pH, and contains oxidizers that enhance thechemical-mechanical removal of Cu at accelerated rates (about 2,000Angstroms per minute or greater). The second step is performed utilizinga selective slurry according to this invention whereby the barrier layeris removed without removing any remaining metal in metal lines andwithout removing the underlying dielectric material. In an alternateembodiment, the second step of the method of this invention is performedutilizing a slurry of this invention that removes the barrier layer andthe dielectric layer without removing any remaining metal in the metallines on the semiconductor substrate. This alternate embodiment isutilized to remove scratches and other defects in the dielectric layerto obtain a smooth polished substrate surface.

[0012] The slurry of this invention is alkaline with a pH in a rangefrom about 7.1, 7.3, 7.5, 8.0, 8.5, 9.0, 9.5, 10, 10.5 to 12. In anembodiment, the pH of the slurry is in a range from about 8.0, 8.1, 8.2,8.3, 8.4, 8.5, 8.6, 8.7, 8.8, 8.9, 9.0, 9.1, 9.2 to 9.5, preferably in arange from about 8.5, 8.6, 8.7, 8.9 to 9.0. In another embodiment, thepH of the slurry is in a range from about 9.5, 9.6, 9.7, 9.8, 9.9, 10,10.1, 10.2, 10.3, 10.4, 10.5, 10.6, 10.7, 10.8 to 11.5, preferably in arange from about 10, 10.1, 10.2, 10.3, 10.4, 10.5, 10.6, 10.7, 10.8 to11.

[0013] The slurry of this invention contains submicron abrasiveparticles with a particle size up to about 50 nm. Preferably theabrasive particles are non-agglomerated and have a particle size fromabout 5, 10, 15, 20, 25, 30, 35, 40, 45 to 50 nm. In an embodiment, thesubmicron abrasive is silica, preferably, colloidal silica.

[0014] Generally, abrasive particles are present in the slurry of thisinvention at about 0.01, 0.1, 0.2, 0.3, 0.4, 0.5, 1, 2, 3, 4, 5, 6, 7,8, 9, 10, 15, 20, 25 to 30% by weight of the slurry. In an embodiment,the abrasive particles are present at about 5, 6, 7, 8, 9, to 9.5% byweight of the slurry, preferably at about 8, 8.1, 8.2, 8.3, 8.4, 8.5,8.6, 8.7, 8.8, 8.9, to 9% by weight of the slurry. In an alternateembodiment, the abrasive particles are present at about 10, 11, 12, 13,14, 15, 16, 17, 18, 19, 20, 25 to 30% by weight of the slurry,preferably at about 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 to 20% byweight of the slurry.

[0015] In an embodiment, the slurry of this invention contains acomplexing agent at about 0.5, 1, 10, 20, 30, 50, 75, 100, 125, 150,175, 200, 300, 400, 500, 600, 700, 1,000, 1,250, 1,500, 1,750, 2,000,2,500, 3,000, 3,500, 4,000, 4,500 to about 5,000 parts per million (ppm)by weight of the slurry, preferably at about 3,000, 3,100, 3,200, 3,300,3,400, 3,500, 3,600, 3,700, 3,800, 3,900, 4,000, 4,500 to about 5,000ppm by weight of the slurry. In an alternate embodiment, the complexingagent is present at about 10, 20, 30, 50, 75, 100, 125, 150, 175, 200,300, 400 to 500 ppm by weight of the slurry, preferably at about 100,125, 150, 175, 200 to 300 ppm by weight of the slurry.

[0016] In an embodiment, a corrosion inhibitor is added to the slurry ofthis invention at about 1, 5, 10, 15, 20, 25, 30, 40, 50, 60, 70, 80,90, 100 to 110 ppm by weight of the slurry, preferably at about 70, 75,80, 85, 90, 95, 100, 105 to 110 ppm by weight of the slurry.

[0017] In an embodiment, an oxidizing agent is added to the slurry ofthis invention at about 1, 100, 500, 750, 1,000, 2,000, 3,000, 4,000,5,000, 6,000, 7,000, 8,000, 9,000, 10,000, 11,000, 12,000, 13,000,14,000 to 15,000 ppm by weight of the slurry, preferably at about 5,000,6,000, 7,000, 8,000, 9,000 to 10,000 ppm by weight of the slurry.

[0018] In an embodiment, the slurry of this invention contains an oxidesuppressant present at about 1, 10, 20, 30, 40, 50, 75, 100, 125, 150,200, 250, 300, 350, 400, 450, 500, 600, 700, 800, 900, 1,000, 1,500,2,000, 2,500, 3,000, 3,500, 4,000, 4,500 to 5,000 ppm by weight of theslurry, preferably at about 1,000, 1,100, 1,200, 1,300, 1,400, 1,500,1,600, 1,700, 1,800, 1,900, 2,000, 2,100, 2,200, 2,300, 2,400, to 2,500ppm by weight of the slurry.

[0019] In an embodiment, the slurry of this invention contains chlorideions at about 0.01, 0.15, 0.2, 0.25, 1, 2, 3, 4, 5, 10, 15, 20, 25, 30,35, 40, 45, 50, 75, 150, 175 to 200 ppm by weight of the slurry, morepreferably at about 50, 75, 100, 125 to 150 ppm by weight of the slurry.

[0020] In an embodiment, the slurry of this invention contains a biocidepresent at about 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110 to 200 ppmby weight of the slurry, preferably at about 90, 100, 110 to 150 ppm byweight of the slurry.

[0021] The method of this invention utilizes a two-step CMP process forpolishing a semiconductor substrate containing a conducting metal layer,a dielectric layer, and a barrier film or layer between the two. In thefirst step of the CMP process, the metal layer is removed from thesubstrate without removing significant amounts of either the barrierfilm or the underlying dielectric layer. In the second step of the CMPprocess, the barrier layer is removed selectively utilizing a slurry ofthis invention without removing the dielectric material or the metal ofthe metal lines in the underlying dielectric layer. In an alternateembodiment, the second step of the CMP process is performed utilizing aslurry according to this invention that is equally highly selective forremoval of the barrier film and the dielectric layer but relatively lessselective for removal of the metal providing metal lines in theunderlying dielectric layer. In this alternate embodiment, the method ofthis invention removes any scratches or defects in the dielectric layer.The second polishing step is performed at an alkaline pH since thebarrier metal removal rate is enhanced in the alkaline range. Typically,barrier metal removal rates above 1000 Angstroms per minute are desiredduring the second polishing step with relatively low dielectric andmetal removal rates. Second-step polishing slurries that are basic andcontain fumed silica are disclosed in U.S. application Ser. No.09/420,682 filed Oct. 19, 1999, which is herein incorporated byreference.

[0022] Abrasives used in CMP slurries include alumina, silica, ceria,germania, titania, zirconia, diamond, boron nitride, boron carbide,silicon carbide and combinations thereof. Preferably, the slurry used inthe method of this invention contains abrasive colloidal silicaparticles. As disclosed in U.S. application Ser. No. 09/439,461 filedNov. 15, 1999, slurries comprised of colloidal silica particles with aprimary particle size of about 10 to about 50 nanometers and a surfacearea of about 40 to about 600 m²/g provide high selectivity for removalof the barrier layer versus the dielectric layer. U.S. application Ser.No. 09/439,461 is herein incorporated by reference.

[0023] The abrasive used in the slurry of this invention has a ZetaPotential of negative (20 millivolts or greater) at the pH of use, i.e.pH>7. Zeta Potential is a measure of surface charge density of abrasiveparticles in dispersion in an aqueous solution of alkaline pH, i.e.pH>7. A more negative Zeta Potential value, typically about −70millivolts to about −20 millivolts is indicative of a better dispersedslurry with none to extremely low levels of agglomeration of abrasiveparticles.

[0024] Typical dielectric materials used in composite semiconductorsubstrates include SiO₂, TEOS, phosphosilicate glass (PSG), boronphosphosilicate glass (BPSG), or a low-k dielectric. Low-k dielectricsinclude porous silica, organic low-k dielectrics such as fluoro polymersand copolymers. Suppression of the dielectric layer removal rate isachieved through passivation of the dielectric layer surface. U.S. Pat.No. 5,614,444, “Method of Using Additives with Silica-Based Slurries toEnhance Selectivity in Metal CMP,” teaches an additive comprising atleast one polar and one apolar component to suppress oxide removal.However, the patent claims the necessity of both a polar and an apolargroup to be present. U.S. Pat. No. 5,391,258 and U.S. Pat. No. 5,738,800teach the use of various compounds to suppress the rate of dielectricremoval during chemical-mechanical polishing of semiconductor substratesand are herein incorporated by reference for all useful purposes. U.S.Pat. No. 5,770,103 teaches the use of mono-, di-, or tri-substitutedphenols for removing a titanium barrier layer from a semiconductorsubstrate and is herein incorporated by reference for all usefulpurposes.

[0025] As disclosed in U.S. application Ser. No. 09/329,225 filed Jun.10, 1999, polishing compositions (i.e. slurries) containing an organicpolymer with a degree of polymerization of 3 and a molecular weightgreater than 10,000 provide a selectivity between the metal and thedielectric layer in excess of 20:1. Exemplary organic polymers for useas oxide suppressants in the slurry of this invention include but arenot limited to poly vinyl alcohol, polyvinyl pyrrolidone, polymethylmethacrylate, poly formaldehyde, poly ethylene glycol andpolymethacrylic acid. U.S. application Ser. No. 09/329,225 is hereinincorporated by reference.

[0026] A complexing agent is added to the slurry of this invention toincrease the solubility of metal residuals on the semiconductorsubstrate at the start of the second CMP polishing step and the barriermetal during the remainder of the second CMP polishing step. U.S.application Ser. No. 09/329,225 provides additional details on themechanism of interaction of complexing agents with metal atoms and alist of compounds for use as complexing agents. Exemplary complexingagents for use in the polishing composition of this invention includeacetic acid, citric acid, ethyl acetoacetate, glycolic acid, lacticacid, malic acid, oxalic acid, salicylic acid, sodium diethyldithiocarbamate, succinic acid, tartaric acid, thioglycolic acid,glycine, alanine, aspartic acid, ethylene diamine, trimethylene diamine,malonic acid, gluteric acid, 3-hydroxybutyric acid, propionic acid,phthalic acid, isophthalic acid, 3-hydroxy salicylic acid, 3,5-dihydroxysalicylic acid, gallic acid, gluconic acid, pyrocatechol, pyrogallol,gallic acid, tannic acid and salts thereof. Preferably, the complexingagent used in the slurry of this invention is citric acid.

[0027] In an embodiment, the polishing composition of this inventioncontains a choride salt. Chloride ions are highly mobile species thatbond to the semiconductor substrate being polished at high surfaceenergy sites such as edges and defects to minimize the local surfaceenergy. Attainment of a uniform surface energy greatly minimizeslocalized non-uniform processes and variations in the surface of thesemiconductor substrate being polished.

[0028] Often oxidizing agents, such as hydrogen peroxide, are added toCMP slurries so that any metal in the substrate being polished isconverted to an oxide during the CMP process thereby enhancing metalremoval rates. A general review of this art is provided by F. Kaufman etal., J. Electrochem. Soc., vol. 138, p. 3460, 1991, incorporated byreference herein. Common oxidizing agents used in slurries are nitrates,iodates, chlorates, perchlorates, chlorites, sulfates, persulfates,peroxides, ozonated water and oxygenated water. Oxidizing agents aretypically used in CMP slurries at about 0.01% (1,000 ppm by weight ofthe slurry) to about 7% (7,000 ppm by weight of the slurry) by weight ofthe slurry. An oxidizing agent is used in the slurry of this inventionto remove metal residuals from the substrate surface and to enhancebarrier layer metal removal rates. Preferably, hydrogen peroxide is usedas the oxidizing agent in the slurry of this invention.

[0029] Corrosion inhibitors are also added to the slurry of thisinvention to prevent static etching of metal in the semiconductorsubstrate. Corrosion inhibitors are typically effective atconcentrations in a range from about 0.001% (100 ppm) to about 4%(40,000 ppm) by weight of the slurry. Suitable corrosion inhibitors foruse in the slurry of this invention include benzotriazole (BTA),mercaptobenzotriazole (MBT), tolyltriazole and other inhibitorstypically used with the metal present in the semiconductor substratebeing polished. Preferably, the corrosion inhibitor used in the slurryof this invention is benzotriazole.

[0030] Biocides are added to the slurry of this invention to preventbacterial and fungal growth. An exemplary biocide being Neolone™Microbicide (major ingredients: 2-methyl-4-isothiazolin-3-one andpropylene glycol) available from Rohm and Haas Company, Philadelphia,Pa. Further information, pertaining to compounds that are suitable foruse as biocides in the polishing composition of this invention, is foundin US Utility Application filed on Feb. 2, 2001 (awaiting a filingreceipt/Serial No. from the US PTO) which claims the benefit of USProvisional Patent Application Serial No. 60/182,960 filed on Feb. 16,2000 which is incorporated herein by reference.

[0031] The ionic strength of the slurry of this invention is adjustedthrough the use of agents such as acids, bases and salts. Exemplaryagents include ammonium hydroxide, ammonium chloride, ammonium bromide,ammonium acetate, ammonium sulfate, citric acid, etc. A suitable ionicstrength is necessary to prevent agglomeration of abrasive particles inthe slurry of this invention. A suitable range of ionic strength in thecontext of this invention is from about 0.01M to 10 M. A lower ionicstrength, up to about 0.01M, is desired in an embodiment of the slurryof this invention having a high abrasive content from about 8 to 30% byweight of the slurry.

[0032] Various embodiments of this invention are illustrated in thefollowing examples.

EXAMPLE 1

[0033] Method 1 in Table 1 refers to a second step method trial that wasperformed utilizing a slurry of this invention and shows high barrierremoval rates with low metal and dielectric removal rates. Method 2 inTable 1 refers to a second step method trial that was performedutilizing a slurry of this invention, and shows high barrier removalrates while metal removal rates are moderate, between high (about 400A/min) and low (about 150 A/min), with a low dielectric removal rate(<250 A/min). TABLE 1 (Å = Angstroms) TaN RR Method (A/min) Ta RR(Å/min) Cu RR (Å/min) SiO₂RR (Å/min) 1 >700 >400 <150 <250 2 >700 >400<150-400 <250

[0034] In each method trial, a Ta removal rate above 400 Å/min and a TaNremoval rate above 700 Å/min was observed. The two methods trials ofTable 1 resulted in good planarity without significant dishing orerosion. The method trials utilized a slurry, according to thisinvention, highly selective to the barrier film (illustrated by highremoval rates of Ta or TaN) and least selective to the metal and thedielectric layer, to provide the first method trial with desiredminimized removal rates of both Cu and SiO₂. The removal rates of Ta orTaN were maximized (>700 Å/min) with a minimized lower removal rate ofCu (<150 Å/min) and SiO₂ (<250 Å/min).

[0035] With proper application of the slurry of this invention,semiconductor substrates can be polished with low observed dishing orrecess of the interconnect structures (metal lines), in particular Cu,as well as low erosion of the underlying dielectric layer (i.e., SiO₂).For example, the second step slurry can be selected according to thisinvention to compensate for any dishing resulting from the first step,by selecting a slurry with an increased selectivity to SiO₂ whichremoves the SiO₂ to the level of the Cu interconnect structures thathave undergone dishing during the first step polishing.

EXAMPLE 2

[0036] Polishing of 6″ wafers containing Cu, TaN, and SiO₂ (TEOS) filmswas performed on a WESTECH 372U polisher (available from IPEC/Planar).An IC1000 XY-grooved primary polishing pad, a Politex Regular Embossedsecondary polishing pad, and a DF200 carrier film were used (allavailable from Rodel, Inc.). A TBW 100 Grit Diamond conditioner wasemployed. The IC grooved pad was mounted on the primary platen of thepolishing machine and 20 precondition sweeps were carried out withdeionized (DI) water to precondition the polishing pad. The conditioningparameters for the primary polishing pad were a downforce (DF) of 7 psi,3 platen sweeps (post with DI water), 70 rpm platen speed, and 75 rpmdisk speed. The Politex pad was mounted to the secondary table andpreconditioned with a 6″ stiff bristle hand brush and DI water with 8scrapes and 8 brushes performed manually. The following conditions wereused during the polishing tests depending on the semiconductor substratebeing polished: TABLE 2 Polishing Test Conditions Parameter First StepSecond Step Time (seconds) 60 10 DF (psi) 2 0.5 Back Pressure (psi) 1 0DF Ramp (sec) 5 5 Carrier (rpm) 60 40 Table (rpm) 60 40 Slurry Flow(ml/min) 150 0 Rinse Off On # polar measurement site map on the CDE andSM-300. Edge exclusion was 10 mm for Cu and 10 for TaN and TEOS.

[0037] TABLE 3 Slurry Formulations Colloidal Particle Silica (wt Slurry¹Diameter % of Tested CA BTA (nm) slurry) pH 1 0.192 0.1 12 8 to 9 8.0 20.192 0.1 12 8 to 9 8.5 3 0.192 0.1 12 8 to 9 9 4 0.192 0.1 12 8 to 99.5 5 0.192 0.1 12 8 to 9 10 6 0.192 0.1 12 8 to 9 10.5

[0038] The slurry formulations listed in Table 3 were utilized to polish6″ wafers containing Cu, TaN, and SiO₂(TEOS). The metal, barrier anddielectric removal rates are summarized in Table 4, along withcalculated selectivity ratios based on the observed removal rates. TABLE4 Removal Rates and Selectivity Ratios SiO₂ Selectivity SelectivitySlurry (TEOS) Ratio Ratio Tested Cu RR TaN RR RR (TaN:Cu) (TaN:TEOS) 155 983 220 17.9:1 4.5:1 2 84 1260 245   15:1 5.1:1 3 86 1411 140 16.4:110.1:1  4 106 1126 175 10.6:1 6.4:1 5 123 1189 187  9.7:1 6.4:1 6 1941305 156  6.7:1 8.4:1

[0039] Slurry formulations, A and B, of this invention are provided inTable 5, with suitable and preferred ranges for various additives, in %or ppm by weight by the slurry. TABLE 5 Slurry Formulations of ThisInvention Preferred Preferred Additive A Range for A B Range for B pH ≧710-11 ≧7 8.5-9.5 Colloidal ≦30 10-20 ≦30 8-9 Silica (%) Complexing ≦500100-300 ≦5,000 3,000-5,000 Agent (ppm) Corrosion ≦110  70-110 ≦110 70-110 Inhibitor Oxidizing ≦15,000  5,000-10,000 — — Agent (ppm)Chloride Salt — — ≦200  50-150 (ppm) Oxide — — ≦5,000 1,000-2,500Suppressant Biocide (ppm) ≦200  90-150 ≦200  90-150

[0040] Although preferred embodiments are disclosed, other embodimentsand modifications of this invention are intended to be covered by thespirit and scope of the appended claims.

What is claimed is:
 1. A method for chemical mechanical polishing (CMP)of a semiconductor substrate having a metal layer, an underlying barrierfilm and an underlying dielectric layer with metal interconnectionstructures, comprising the steps of: removing the metal layer by firststep CMP utilizing a first step slurry that is highly selective to themetal of the metal layer and less selective to the barrier material ofthe barrier film to remove the metal of the metal layer with a maximizedrate of metal removal by polishing, and to minimize removal of thebarrier material of the barrier film; and removing the barrier materialby second step CMP utilizing a second step slurry that is highlyselective to the barrier material and is least selective to the metallayer and the dielectric layer, to remove the barrier film with amaximized rate by polishing, with minimized removal of the metal of themetal layer and minimized removal of the dielectric layer to provide theheight of the dielectric layer at a surface level with the metalinterconnection structures; wherein said second step slurry has a pHgreater than
 7. 2. The method as recited in claim 1, wherein the step ofremoving the barrier film by second step CMP utilizes a second stepslurry having a pH greater than 7, and a dispersion of colloidal silicahaving a Zeta Potential of negative (20 millivolts or greater) at saidpH.
 3. The method as recited in claim 1, wherein the step of removingthe barrier film by second step CMP utilizes a second step slurry havinga pH greater than 7, and submicron abrasive particles of colloidalsilica comprising up to about 30% by weight of said second step slurry.4. The method as recited in claim 1, wherein the step of removing thebarrier film by second step CMP utilizes a second step slurry having apH greater than 7, a dispersion of colloidal silica having a zetapotential of negative (20 millivolts or greater) at said pH, andsubmicron abrasive particles of colloidal silica comprising up to about30% by weight of said second step slurry.
 5. The method as recited inclaim 1, wherein the step of removing the barrier film by second stepCMP utilizes a second step slurry; wherein said second step slurrycomprises: submicron abrasive partices of colloidal silica comprising upto about 30% by weight of said second step slurry; a complexing agent upto about 5,000 ppm by weight of said second step slurry; a corrosioninhibitor up to about 110 ppm by weight of said second step slurry; abiocide up to about 200 ppm by weight of said second step slurry; anoxidizing agent up to about 15,000 ppm by weight of said second stepslurry; an oxide suppressant up to about 5,000 ppm by weight of saidsecond step slurry; and a chloride salt up to about 200 ppm by weight ofsaid second step slurry.
 6. The method as recited in claim 5, whereinthe step of removing the barrier film by second step CMP utilizes saidsecond step slurry having a Zeta Potential of negative (20 millivolts orgreater) at said pH.
 7. The method as recited in claim 5, wherein thestep of removing the barrier film by second step CMP utilizes a secondstep slurry having a complexing agent selected from the group consistingof: malic acid, tartaric acid, gluconic acid, glycolic acid, citricacid, phthalic acid, pyrocatechol, pyrogallol, gallic acid, and tannicacid.
 8. The method as recited in claim 5, wherein the step of removingthe barrier film by second step CMP utilizes a second step slurry havinga copper corrosion inhibitor.
 9. The method as recited in claim 5,wherein the step of removing the barrier film by second step CMPutilizes a second step slurry having hydrogen peroxide as the oxidizingagent.
 10. The method as recited in claim 5, wherein the step ofremoving the barrier film by second step CMP utilizes a second stepslurry having ammonium chloride as the chloride salt.
 11. The method asrecited in claim 5, wherein the step of removing the barrier film bysecond step CMP utilizes a second step slurry havingpolyvinylpyrrolidone as the oxide suppressant.
 12. A method forpolishing a semiconductor substrate having a metal layer, an underlyingbarrier film and an underlying dielectric layer with metal interconnectstructures, comprising the steps of: removing the metal layer by firststep CMP utilizing a first step slurry that is highly selective to themetal of the metal layer and less selective to the barrier film toremove the metal of the metal layer with a maximized rate of metalremoval by polishing, and to minimize removal of the barrier film; andremoving the dielectric layer and barrier film by second step CMPutilizing a second step slurry that is equally highly selective to thebarrier material and the dielectric material and least selective to themetal in the metal layer; wherein said second step slurry comprises a pHgreater than 7; submicron abrasive partices of colloidal silicacomprising up to about 30% by weight of said second step slurry; acomplexing agent up to about 5,000 ppm by weight of said second stepslurry; a corrosion inhibitor up to about 110 ppm by weight of saidsecond step slurry; a biocide up to about 200 ppm by weight of saidsecond step slurry; and an oxidizing agent up to about 15,000 ppm byweight of said second step slurry.
 13. The method as recited in claim12, wherein the step of removing the barrier film or alternately thedielectric material by second step CMP utilizes said second step slurryhaving a Zeta potential of negative (20 millivolts or greater) at saidpH.
 14. The method as recited in claim 12, wherein the step of removingthe barrier film or alternately the dielectric material by second stepCMP utilizes a second step slurry having a complexing agent selectedfrom the group consisting of: malic acid, tartaric acid, gluconic acid,glycolic acid, citric acid, phthalic acid, pyrocatechol, pyrogallol,gallic acid, and tannic acid.
 15. The method as recited in claim 12,wherein the step of removing the barrier film or alternately thedielectric material by second step CMP utilizes a second step slurryhaving a copper corrosion inhibitor.
 16. The method as recited in claim12, wherein the step of removing the barrier film by second step CMPutilizes a second step slurry having hydrogen peroxide as the oxidizer.17. An aqueous polishing composition for polishing semiconductorsubstrates comprising: a pH greater than 7; submicron abrasive particesof colloidal silica comprising up to about 30% by weight of said secondstep slurry; a complexing agent up to about 5,000 ppm by weight of saidsecond step slurry; a corrosion inhibitor up to about 110 ppm by weightof said second step slurry; a biocide up to about 200 ppm by weight ofsaid second step slurry; an oxidizing agent up to about 15,000 ppm byweight of said second step slurry; an oxide suppressant up to about5,000 ppm by weight of said second step slurry; and a chloride salt upto about 200 ppm by weight of said second step slurry.
 18. A polishingcomposition according to claim 17 wherein said complexing agent iscitric acid.
 19. A polishing composition according to claim 17 whereinsaid corrosion inhibitor is selected from a group consisting ofbenzotriazole, tolyltriazole and mixtures thereof.
 20. A polishingcomposition according to claim 17 wherein the oxidizing agent ishydrogen peroxide.
 21. A polishing composition according to claim 17wherein the chloride salt is ammonium chloride.
 22. An aqueous polishingcomposition for polishing semiconductor substrates comprising a pHgreater than 7; submicron abrasive partices of colloidal silicacomprising up to about 30% by weight of said second step slurry; acomplexing agent up to about 5,000 ppm by weight of said second stepslurry; a corrosion inhibitor up to about 110 ppm by weight of saidsecond step slurry; a biocide up to about 200 ppm by weight of saidsecond step slurry; and an oxidizing agent up to about 15,000 ppm byweight of said second step slurry.
 23. A polishing composition accordingto claim 22 wherein said complexing agent is citric acid.
 24. Apolishing composition according to claim 22 wherein said corrosioninhibitor is selected from a group consisting of benzotriazole,tolyltriazole and mixtures thereof.
 25. A polishing compositionaccording to claim 22 wherein the oxidizing agent is hydrogen peroxide.